1. Field of the Invention
The present invention relates to radio frequency and intermediate frequency communications systems, and more particularly to intermediate frequency gain stage circuitry and rectifying circuitry of a radio frequency system receiver.
2. Description of the Related Art
With the dramatic advances of deep submicron CMOS technology, the ability to integrate more and more radio functions into one piece of silicon is becoming possible. Radio functions within integrated circuits are generally partitioned into either an RF (radio frequency) chip and an IF (intermediate frequency) chip, or are partitioned into independent transmitter and receiver chips. Traditionally, RF and IF chips have been implemented in a BiCMOS, Bipolar, or Gallium Arsenide (GA) technology. However, more recently, these functions are being implemented in CMOS technology.
FIG. 1 is a block diagram that illustrates a typical sub-section of an IF system. The basic function of the sub-section is to provide large amounts of gain between the differential inputs, IM and IP, and differential outputs, OP and OM, and to produce a linear output on node IOUT with logarithmic changes of power on the inputs IP and IM. An IF signal path is therefore formed between the differential inputs IM and IP and differential outputs OP and OM. The function of the IF signal path is to prepare the relatively low amplitude incoming signal for demodulation by giving it many decibels of gain and filtering. The linear output on node IOUT is used to generate a receive signal strength indicator (RSSI) signal which is typically employed for choosing an incoming channel that has the highest strength and yields the optimum signal to noise performance for the receiver. The voltage range, or power range, of the incoming signal varies so greatly that a logarithmic RSSI is required to function within the limited voltage range of integrated circuits.
The IF signal path of the limiter includes a plurality of serially coupled gain stages 11A-11E. Each limiter stage 11 has a fixed amount of gain, such as 12 db, and a limited voltage swing, such as 0.4 volts. As the input power increases on the inputs IP and IM, the last limiter stage 11E will reach clipping first. Likewise, limiter stages 11D, 11C, 11B and 11A will each reach a clipping level in order in intervals of the interstage gain. The intent of the IF signal path is to produce a voltage-limited square-wave like output signal on outputs OP and OM that can be converted to digital logic levels with a simple comparator.
The circuitry used to generate the linear output on node IOUT includes a plurality of RSSI rectifying stages 13A-13E. Each RSSI rectifying stage 13 operates similar to the gain stages II in the IF signal path, but outputs a limited rectified current at intervals of the interstage gain. Rectifying stage 13E is the first output stage to output a limited rectified current as a function of the input power, and rectifying stages 13D, 13C, 13B and 13A each follow with corresponding increases in input power. By terminating node IOUT into a resistive load, the rectified current is converted into a rectified voltage. The effect of cascading multiple current-limited rectifying stages creates a piecewise linear approximation of a logarithmic function. FIG. 2 depicts the RSSI function as a function of input power and FIG. 3 illustrates the transient response on the last three gain stages 11C, 11D and 11E of the IF signal path for a fixed sinusoidal input.
FIGS. 4 and 5 are schematic diagrams that illustrate circuitry for implementing each gain stage and each rectifying stage 13, respectively, of the IF system of FIG. 1. The limiter stage 11 of FIG. 4 is a simple differential-pair circuit with a diode-connected load, where the input pair transistors MN1 and MN2 are of the same type as the load transistors MN3 and MN4. The basic idea of this architecture is to get a voltage gain relationship from the gm of transistors MN1 and MN2 to the gm of transistors MN3 and MN4. This performs well from an AC perspective but has limitations with respect to the common-mode voltage. In order to get more gain from the circuit, the size of transistors MN3 and MN4 must be decreased or the current through transistors MN1 and MN2 must be increased. By increasing the tail current in transistor MN0, the current through transistors MN1 and MN2 may be increased, but the gain will not change appreciably because the same current is in the loads MN3 and MN4. Hence, the best way to increase gain is to increase the ratio of transistor size MN1 and MN2 with respect to the size of transistors MN3 and MN4. This creates another difficulty in that the input-pair transistors MN1 and MN2 desirably operate with a common mode voltage closer to the supply voltage AVCC. However, as transistors MN3 and MN4 are decreased in size the drain to source voltage increases and forces transistors MN1 and MN2 to operate with a common mode voltage closer to a VSS. The effects of input and output common mode voltage can best be seen by cascading multiple gain stages as illustrated in FIG. 1. This results in design tradeoffs between gain and common-mode operation, thus create difficulties for a manufacturable circuit.
The rectifying circuit of FIG. 5 performs the current rectification and limiting function of each rectifying stage 13 of FIG. 1. When the input signal is not present, the circuit produces a constant output current, Ir, which is proportional to the differential tail current "I". The tail-current I is divided between the first differential pair of transistors MN5 and MN6 and further divided between the second differential pair formed with transistors MN1, MN2, MN3, and MN4. The p-channel diode-connected transistors MP1 and MP2 define the loads for the second differential pair devices. The use of two differential pair circuits and the redirection of current for positive and negative input signals create the rectified output signal on IOUT. Lastly, the implementation of using one common tail-current elegantly produces a current-limited output as well. This circuit can perform adequately, but it is difficult to bias both sets of input pair devices, and the fact that it uses a completely different gain stage from the IF signal path induces potential problems. Furthermore, this circuit does not use any casecode structures. Thus, current mirroring mismatches and reduced power supply rejection can lead to reduction in the overall system performance.